1. Technical Field
The embodiments described herein relate to a semiconductor circuit technique, and more particularly, to a write driving circuit and a semiconductor memory apparatus using the same.
2. Related Art
In general, as shown in FIG. 1, conventional semiconductor memory apparatus include a cell core, a bit line sense amplifier BLSA, switching transistors Ma and Mb, a write driver WDRV, and an IO sense amplifier IOSA.
The cell core is formed in a matrix of bit lines BL and BLB and word lines WL, and includes a plurality of cells each having transistors and capacitors connected to the bit lines BL and BLB and the word lines WL.
The bit line sense amplifier BLSA senses and amplifies data transmitted through the bit lines BL and BLB, and transmits the amplified data to local signal lines LIO and LIOB.
The switching transistors Ma and Mb connect the bit lines BL and BLB and the bit line sense amplifier BLSA according to a column selection signal ‘YS’, respectively.
The write driver WDRV transmits data that is transmitted from the outside of the semiconductor memory apparatus through global lines GIO and GIOB to the bit line sense amplifier 20 through the local signal lines LIO and LIOB.
The IO sense amplifier IOSA transmits data output from the cell core through the sense amplifier BLSA to the global signal lines GIO and GIOB.
Recent increases in the storage capacity of conventional semiconductor memory apparatus makes it difficult to control the entire cell core. Therefore, in order to improve the efficiency of control, the cell core is divided into a plurality of memory banks.
The memory bank may include some of the cells of the cell core, a circuit for writing or reading data on or from the cells, and signal lines, that is, components except for the cell core shown in FIG. 1.
For example, as shown in FIG. 2, a conventional semiconductor memory apparatus includes a plurality of memory banks (bank Nos. 0 to 3), a write driving circuit 200, global signal lines GIO and GIOB, and local signal lines LIO and LIOB.
The global signal lines GIO and GIOB are provided to transmit data input from the outside of the semiconductor memory apparatus to the write driving circuit 200. The local signal lines LIO and LIOB are provided to transmit data input to the write driving circuit 200 through the global signal lines GIO and GIOB to the plurality of memory banks (bank Nos. 0 to 3).
The write driving circuit 200 includes a plurality of write drivers WDRV. The write drivers WDRV are assigned to the corresponding memory banks (bank Nos. 0 to 3).
The number of write drivers WDRV used in each of the memory banks (bank Nos. 0 to 3) depends on an input/output structure and a prefetch method employed in a corresponding product. For example, when the input/output structure is ×32 and an 8-bit prefetch method is used, 256 write drivers WDRV are provided in each memory bank so that 256-bit data can be written with one write command. In addition, FIG. 2 shows a semiconductor memory apparatus having four memory banks. The number of banks depends on the capacity of the semiconductor memory apparatus.
Referring to FIG. 2, a plurality of write drivers 210 are assigned to bank No. 0, a plurality of write drivers 220 are assigned to bank No. 1, a plurality of write drivers 230 are assigned to bank No. 2, and a plurality of write drivers 240 are assigned to bank No. 3.
Each of the plurality of write drivers 210 to 240 have the same structure, and as shown in FIG. 3, the write driver 210 includes a detecting unit 211 and a driving unit 212.
The detecting unit 211 detects the levels of data transmitted through the global signal lines GIO and GIOB and outputs detection signals ‘LAT’, ‘DRV’, ‘LATB’, and ‘DRVB’.
The driving unit 212 drives the local signal lines LIO and LIOB at the detected data level on the basis of the detection signals ‘LAT’, ‘DRV’, ‘LATB’, and ‘DRVB’, and pre-charges the local signal lines LIO and LIOB according to a pre-charge signal ‘LIOPCG’ and a bank write enable signal BWEN. The pre-charge signal ‘LIOPCG’ maintains the local signal lines LIO and LIOB at a bit line pre-charge voltage VBLP. The bank write enable signal ‘BWEN’ sets a write period.
Next, the operation of a conventional semiconductor memory apparatus, such as that illustrated in FIGS. 1-3, will be described in detail.
A write command is input from the outside of the semiconductor memory apparatus, and data corresponding to the write command is input to the global signal lines GIO and GIOB.
When the bank write enable signal ‘BWEN’ is activated at a high level, the detecting unit 211 detects data input to the global lines GIO and GIOB, and outputs the detection signals ‘LAT’, ‘DRV’, ‘LATB’, and ‘DRVB’. The pre-charge signal ‘LIOPCG’ is deactivated at a low level during a period for which the bank write enable signal ‘BWEN’ is in an active state.
The driving unit 212 drives the local signal lines LIO and LIOB at the levels of the global signal lines GIO and GIOB according to the detection signals‘LAT’, ‘DRV’,‘LATB’, and ‘DRVB’.
In the driving unit 212, when the pre-charge signal ‘LIOPCG’ is deactivated at a low level, or when the bank write enable signal ‘BWEN’ is activated at a high level, a NAND gate ND1 and an inverter IV8 output high-level and low-level signals, respectively.
When the NAND gate ND1 and the inverter IV8 output the high-level and low-level signals, respectively, transistors M17 to M22 are all turned off, so that the pre-charge operation stops.
Meanwhile, when the pre-charge signal ‘LIOPCG’ is activated at a high level, or when the bank write enable signal ‘BWEN’ is deactivated in a low level, the NAND gate ND1 and the inverter IV8 output low-level and high-level signals, respectively.
When the NAND gate ND1 and the inverter IV8 output the low-level and high-level signals, respectively, the transistors M17 to M22 are all turned on, so that the local signal lines LIO and LIOB are pre-charged with the bit line pre-charge voltage VBLP.
As mentioned, a conventional semiconductor memory apparatus includes a plurality of write drivers. Each of the write drives includes a circuit structure for detecting data and another circuit structure for driving data. Therefore, the write drivers take up a lot of space in the semiconductor memory apparatus, and the number of necessary write drivers increases as the capacity of the semiconductor memory apparatus becomes large. The space requirement associated with a conventional write driver makes it difficult to layout a conventional semiconductor memory apparatus, and causes a reduction in the efficiency of cells and a net die, and an increase in the size of the semiconductor memory apparatus.